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1. general description the 74hc4053-q100; 74hct4053-q100 is a high -speed si-gate cmos device and is pin compatible with low-power schottky ttl (l sttl). it is specified in compliance with jedec standard no. 7a. the 74hc4053-q100; 74hct4053-q100 is triple 2-channel analog multiplexer/demultiplexer wit h a common enable input (e ). each multiple xer/demultiplexer has two independent inputs/outputs (ny0 and ny1), a common input/output (nz) and three digital select inputs (sn). with e low, one of the two switches is selected (low-impedance on-state) by s1 to s3. with e high, all switches are in the high-impedance off-state, independent of s1 to s3. v cc and gnd are the supply voltage pins for the digital control inputs (s0 to s2, and e ). the v cc to gnd ranges are 2.0 v to 10.0 v for 74hc4053-q100, and 4.5 v to 5.5 v for 74hct4053-q100. the analog inputs/outputs (ny0 to ny1, and nz) can swing between v cc as a positive limit and v ee as a negative limit. v cc ? v ee may not exceed 10.0 v. for operation as a digital mu ltiplexer/demu ltiplexer, v ee is connected to gnd (typically ground). this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? wide analog input voltage range from ? 5 v to +5 v ? low on resistance: ? 80 ? (typical) at v cc ? v ee =4.5v ? 70 ? (typical) at v cc ? v ee =6.0v ? 60 ? (typical) at v cc ? v ee =9.0v ? logic level translation: to enabl e 5 v logic to communicate with ? 5 v analog signals ? typical ?break before make? built-in ? esd protection: ? mil-std-883, method 3015 exceeds 2000 v ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) ? cdm aec-q100-011 revision b exceeds 1000 v ? multiple package options 74hc4053-q100; 74hct4053-q100 triple 2-channel analog multiplexer/demultiplexer rev. 2 ? 22 november 2012 product data sheet
74hc_hct4053_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 2 ? 22 november 2012 2 of 30 nxp semiconductors 74hc4053-q100; 74hct4053-q100 triple 2-channel analog multiplexer/demultiplexer 3. applications ? analog multiplexing and demultiplexing ? digital multiplexing and demultiplexing ? signal gating 4. ordering information table 1. ordering information type number package temperature range name description version 74HC4053D-Q100 ? 40 ? c to +125 ? c so16 plastic small outline package; 16 leads; body width 3.9 mm sot109-1 74hct4053d-q100 74hc4053pw-q100 ? 40 ? c to +125 ? c tssop16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 74hct4053pw-q100 74hc4053bq-q100 ? 40 ? c to +125 ? c dhvqfn16 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 ? 3.5 ? 0.85 mm sot763-1 74hct4053bq-q100
74hc_hct4053_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 2 ? 22 november 2012 3 of 30 nxp semiconductors 74hc4053-q100; 74hct4053-q100 triple 2-channel analog multiplexer/demultiplexer 5. functional diagram fig 1. functional diagram 001aak341 logic level conversion 11 16 v cc 13 1y1 s1 logic level conversion decoder logic level conversion 12 1y0 14 1z 1 2y1 2 2y0 15 2z 3 3y1 5 3y0 43z 10 s2 9 87 v ee gnd s3 6 e fig 2. logic symbol fig 3. iec logic symbol 001aae125 1y0 12 1y1 s1 13 11 s210 s39 6 e 2y0 2 2y1 1 3y0 5 3y1 3 3z 4 2z 15 1z 14 001aae126 6 en 11 # # # mux/dmux 12 13 0 1 0/1 0 1 14 10 2 1 15 9 5 3 4
74hc_hct4053_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 2 ? 22 november 2012 4 of 30 nxp semiconductors 74hc4053-q100; 74hct4053-q100 triple 2-channel analog multiplexer/demultiplexer 6. pinning information 6.1 pinning fig 4. schematic diagram (one switch) 001aad544 from logic v cc v ee v ee v cc v cc v ee y z v cc (1) this is not a supply pin. the substrate is attached to this pad using conductive die atta ch material. there is no electrical or mechanical requi rement to solder this pad. however, if it is soldered, the solder land should remain floating or be connected to vcc. fig 5. pin configuration so16 and tssop16 fig 6. pin configuration dhvqfn16 74hc4053-q100 74hct4053-q100 2y1 v cc 2y0 2z 3y1 1z 3z 1y1 3y0 1y0 es 1 v ee s2 gnd s3 aaa-003164 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 aaa-003165 v ee s2 es 1 3y0 1y0 3z 1y1 3y1 1z 2y0 2z gnd s3 2y1 v cc transparent top view 7 10 6 11 5 12 4 13 3 14 2 15 8 9 1 16 terminal 1 index area v cc (1) 74hc4053-q100 74hct4053-q100
74hc_hct4053_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 2 ? 22 november 2012 5 of 30 nxp semiconductors 74hc4053-q100; 74hct4053-q100 triple 2-channel analog multiplexer/demultiplexer 6.2 pin description 7. functional description [1] h = high voltage level; l = low voltage level; x = don?t care. 8. limiting values [1] to avoid drawing v cc current out of terminal nz, when switch current flows in to terminals nyn, the voltage drop across the bidirectional switch must not exceed 0.4 v. if the switch current flows into terminal nz, no v cc current flows out of terminals nyn. in this case, there is no limit for the voltage drop across the switch, but the voltages at nyn and nz may not exceed v cc or v ee . [2] for so16 package: above 70 ? c the value of p tot derates linearly with 8 mw/k. for tssop16 package: above 60 ? c the value of p tot derates linearly with 5.5 mw/k. for dhvqfn16 package: above 60 ? c the value of p tot derates linearly with 4.5 mw/k. table 2. pin description symbol pin description e 6 enable input (active low) v ee 7 supply voltage gnd 8 ground supply voltage s1, s2, s3 11, 10, 9 select input 1y0, 2y0, 3y0 12, 2, 5 i ndependent input or output 1y1, 2y1, 3y1 13, 1, 3 i ndependent input or output 1z, 2z, 3z 14, 15, 4 common output or input v cc 16 supply voltage table 3. function table [1] inputs channel on e sn llny0 to nz l h ny1 to nz h x switches off table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to v ss = 0 v (ground). symbol parameter conditions min max unit v cc supply voltage [1] ? 0.5 +11.0 v i ik input clamping current v i < ? 0.5 v or v i >v cc +0.5v - ? 20 ma i sk switch clamping current v sw < ? 0.5 v or v sw >v cc +0.5v - ? 20 ma i sw switch current ? 0.5 v < v sw 74hc_hct4053_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 2 ? 22 november 2012 6 of 30 nxp semiconductors 74hc4053-q100; 74hct4053-q100 triple 2-channel analog multiplexer/demultiplexer 9. recommended operating conditions table 5. recommended operating conditions symbol parameter conditions 74hc4053-q100 74hct4053-q100 unit min typ max min typ max v cc supply voltage see figure 7 and figure 8 v cc ? gnd 2.0 5.0 10.0 4.5 5.0 5.5 v v cc ? v ee 2.0 5.0 10.0 2.0 5.0 10.0 v v i input voltage gnd - v cc gnd - v cc v v sw switch voltage v ee -v cc v ee -v cc v t amb ambient temperature ? 40 +25 +125 ? 40 +25 +125 ?c ? t/ ? v input transition rise and fall rate v cc = 2.0 v - - 625 - - - ns/v v cc = 4.5 v - 1.67 139 - 1.67 139 ns/v v cc =6.0v - - 83 - - - ns/v v cc = 10.0 v - - 31 - - - ns/v fig 7. guaranteed operating area as a function of the supply voltages for 74hc4053-q100 fig 8. guaranteed operating area as a function of the supply voltages for 74hct4053-q100 v cc ? v ee (v) 010 8 46 2 001aad545 4 6 2 8 10 0 operating area v cc ? gnd (v) v cc ? v ee (v) 010 8 46 2 001aad546 4 6 2 8 10 0 v cc ? gnd (v) operating area
74hc_hct4053_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 2 ? 22 november 2012 7 of 30 nxp semiconductors 74hc4053-q100; 74hct4053-q100 triple 2-channel analog multiplexer/demultiplexer 10. static characteristics table 6. r on resistance per switch for 74hc4053-q100 and 74hct4053-q100 v i = v ih or v il ; for test circuit see figure 9 . v is is the input voltage at a nyn or nz terminal, whichever is assigned as an input. v os is the output voltage at a nyn or nz termi nal, whichever is assigned as an output. for 74hc4053-q100: v cc ? gnd or v cc ? v ee = 2.0v, 4.5v, 6.0v and 9.0v. for 74hct4053-q100: v cc ? gnd = 4.5 v and 5.5 v, v cc ? v ee = 2.0 v, 4.5 v, 6.0 v and 9.0 v. symbol parameter conditions min typ max unit t amb =25 ?c r on(peak) on resistance (peak) v is =v cc to v ee v cc = 2.0 v; v ee = 0 v; i sw = 100 ? a [1] --- ? v cc = 4.5 v; v ee = 0 v; i sw = 1000 ? a-100180 ? v cc = 6.0 v; v ee = 0 v; i sw = 1000 ? a-90160 ? v cc = 4.5 v; v ee = ? 4.5 v; i sw = 1000 ? a-70130 ? r on(rail) on resistance (rail) v is =v ee v cc = 2.0 v; v ee = 0 v; i sw = 100 ? a [1] -150- ? v cc = 4.5 v; v ee = 0 v; i sw = 1000 ? a-80140 ? v cc = 6.0 v; v ee = 0 v; i sw = 1000 ? a-70120 ? v cc = 4.5 v; v ee = ? 4.5 v; i sw = 1000 ? a-60105 ? v is =v cc v cc = 2.0 v; v ee = 0 v; i sw = 100 ? a [1] -150- ? v cc = 4.5 v; v ee = 0 v; i sw = 1000 ? a-90160 ? v cc = 6.0 v; v ee = 0 v; i sw = 1000 ? a-80140 ? v cc = 4.5 v; v ee = ? 4.5 v; i sw = 1000 ? a-65120 ? ? r on on resistance mismatch between channels v is =v cc to v ee v cc = 2.0 v; v ee = 0 v [1] --- ? v cc = 4.5 v; v ee = 0 v - 9 - ? v cc = 6.0 v; v ee = 0 v - 8 - ? v cc = 4.5 v; v ee = ? 4.5 v - 6 - ? t amb = ? 40 ? cto+85 ?c r on(peak) on resistance (peak) v is =v cc to v ee v cc = 2.0 v; v ee = 0 v; i sw = 100 ? a [1] --- ? v cc = 4.5 v; v ee = 0 v; i sw = 1000 ? a --225 ? v cc = 6.0 v; v ee = 0 v; i sw = 1000 ? a --200 ? v cc = 4.5 v; v ee = ? 4.5 v; i sw = 1000 ? a --165 ?
74hc_hct4053_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 2 ? 22 november 2012 8 of 30 nxp semiconductors 74hc4053-q100; 74hct4053-q100 triple 2-channel analog multiplexer/demultiplexer [1] when supply voltages (v cc ? v ee ) near 2.0 v the analog switch on resistance be comes extremely non-linear. when using a supply of 2 v, only use these devices fo r transmitting digital signals. r on(rail) on resistance (rail) v is =v ee v cc = 2.0 v; v ee = 0 v; i sw = 100 ? a [1] --- ? v cc = 4.5 v; v ee = 0 v; i sw = 1000 ? a --175 ? v cc = 6.0 v; v ee = 0 v; i sw = 1000 ? a --150 ? v cc = 4.5 v; v ee = ? 4.5 v; i sw = 1000 ? a --130 ? v is =v cc v cc = 2.0 v; v ee = 0 v; i sw = 100 ? a [1] --- ? v cc = 4.5 v; v ee = 0 v; i sw = 1000 ? a --200 ? v cc = 6.0 v; v ee = 0 v; i sw = 1000 ? a --175 ? v cc = 4.5 v; v ee = ? 4.5 v; i sw = 1000 ? a --150 ? t amb = ? 40 ? c to +125 ?c r on(peak) on resistance (peak) v is =v cc to v ee v cc = 2.0 v; v ee = 0 v; i sw = 100 ? a [1] --- ? v cc = 4.5 v; v ee = 0 v; i sw = 1000 ? a --270 ? v cc = 6.0 v; v ee = 0 v; i sw = 1000 ? a --240 ? v cc = 4.5 v; v ee = ? 4.5 v; i sw = 1000 ? a --195 ? r on(rail) on resistance (rail) v is =v ee v cc = 2.0 v; v ee = 0 v; i sw = 100 ? a [1] --- ? v cc = 4.5 v; v ee = 0 v; i sw = 1000 ? a --210 ? v cc = 6.0 v; v ee = 0 v; i sw = 1000 ? a --180 ? v cc = 4.5 v; v ee = ? 4.5 v; i sw = 1000 ? a --160 ? v is =v cc v cc = 2.0 v; v ee = 0 v; i sw = 100 ? a [1] --- ? v cc = 4.5 v; v ee = 0 v; i sw = 1000 ? a --240 ? v cc = 6.0 v; v ee = 0 v; i sw = 1000 ? a --210 ? v cc = 4.5 v; v ee = ? 4.5 v; i sw = 1000 ? a --180 ? table 6. r on resistance per switch for 74hc4053-q100 and 74hct4053-q100 ?continued v i = v ih or v il ; for test circuit see figure 9 . v is is the input voltage at a nyn or nz terminal, whichever is assigned as an input. v os is the output voltage at a nyn or nz termi nal, whichever is assigned as an output. for 74hc4053-q100: v cc ? gnd or v cc ? v ee = 2.0v, 4.5v, 6.0v and 9.0v. for 74hct4053-q100: v cc ? gnd = 4.5 v and 5.5 v, v cc ? v ee = 2.0 v, 4.5 v, 6.0 v and 9.0 v. symbol parameter conditions min typ max unit
74hc_hct4053_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 2 ? 22 november 2012 9 of 30 nxp semiconductors 74hc4053-q100; 74hct4053-q100 triple 2-channel analog multiplexer/demultiplexer v is =0vto(v cc ? v ee ). v is =0vto(v cc ? v ee ). (1) v cc =4.5v (2) v cc =6v (3) v cc =9v fig 9. test circuit for measuring r on fig 10. typical r on as a function of input voltage v is v 001aah826 nyn sn from select input nz gnd v ee v cc v is i sw v sw v is (v) 0 9.0 7.2 3.6 5.4 1.8 mnb047 50 70 30 90 110 10 r on () (1) (2) (3) r on v sw i sw -------- - = table 7. static characte ristics for 74hc4053-q100 voltages are referenced to gnd (ground = 0 v). v is is the input voltage at pins nyn or nz, whichever is assigned as an input. v os is the output voltage at pins nz or nyn, whichever is assigned as an output. symbol parameter conditions min typ max unit t amb =25 ?c v ih high-level input voltage v cc = 2.0 v 1.5 1.2 - v v cc = 4.5 v 3.15 2.4 - v v cc = 6.0 v 4.2 3.2 - v v cc = 9.0 v 6.3 4.7 - v v il low-level input voltage v cc = 2.0 v - 0.8 0.5 v v cc = 4.5 v - 2.1 1.35 v v cc = 6.0 v - 2.8 1.8 v v cc = 9.0 v - 4.3 2.7 v i i input leakage current v ee = 0 v; v i =v cc or gnd v cc = 6.0 v - - ? 0.1 ? a v cc = 10.0 v - - ? 0.2 ? a i s(off) off-state leakage current v cc = 10.0 v; v ee = 0 v; v i =v ih or v il ; ?v sw ? =v cc ? v ee ; see figure 11 per channel - - ? 0.1 ? a all channels - - ? 0.1 ? a i s(on) on-state leakage current v i =v ih or v il ; ?v sw ? =v cc ? v ee ; v cc = 10.0 v; v ee = 0 v; see figure 12 -- ? 0.1 ? a
74hc_hct4053_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 2 ? 22 november 2012 10 of 30 nxp semiconductors 74hc4053-q100; 74hct4053-q100 triple 2-channel analog multiplexer/demultiplexer i cc supply current v ee = 0 v; v i =v cc or gnd; v is =v ee or v cc ; v os =v cc or v ee v cc = 6.0 v - - 8.0 ? a v cc = 10.0 v - - 16.0 ? a c i input capacitance - 3.5 - pf c sw switch capacitance independent pins nyn - 5 - pf common pins nz - 8 - pf t amb = ? 40 ? cto+85 ?c v ih high-level input voltage v cc = 2.0 v 1.5 - - v v cc = 4.5 v 3.15 - - v v cc = 6.0 v 4.2 - - v v cc = 9.0 v 6.3 - - v v il low-level input voltage v cc = 2.0 v - - 0.5 v v cc = 4.5 v - - 1.35 v v cc = 6.0 v - - 1.8 v v cc = 9.0 v - - 2.7 v i i input leakage current v ee = 0 v; v i =v cc or gnd v cc = 6.0 v - - ? 1.0 ? a v cc = 10.0 v - - ? 2.0 ? a i s(off) off-state leakage current v cc = 10.0 v; v ee = 0 v; v i =v ih or v il ; ?v sw ? =v cc ? v ee ; see figure 11 per channel - - ? 1.0 ? a all channels - - ? 1.0 ? a i s(on) on-state leakage current v i =v ih or v il ; ?v sw ? =v cc ? v ee ; v cc = 10.0 v; v ee = 0 v; see figure 12 -- ? 1.0 ? a i cc supply current v ee = 0 v; v i =v cc or gnd; v is =v ee or v cc ; v os =v cc or v ee v cc = 6.0 v - - 80.0 ? a v cc = 10.0 v - - 160.0 ? a t amb = ? 40 ? c to +125 ?c v ih high-level input voltage v cc = 2.0 v 1.5 - - v v cc = 4.5 v 3.15 - - v v cc = 6.0 v 4.2 - - v v cc = 9.0 v 6.3 - - v v il low-level input voltage v cc = 2.0 v - - 0.5 v v cc = 4.5 v - - 1.35 v v cc = 6.0 v - - 1.8 v v cc = 9.0 v - - 2.7 v table 7. static characte ristics for 74hc4053-q100 ?continued voltages are referenced to gnd (ground = 0 v). v is is the input voltage at pins nyn or nz, whichever is assigned as an input. v os is the output voltage at pins nz or nyn, whichever is assigned as an output. symbol parameter conditions min typ max unit
74hc_hct4053_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 2 ? 22 november 2012 11 of 30 nxp semiconductors 74hc4053-q100; 74hct4053-q100 triple 2-channel analog multiplexer/demultiplexer i i input leakage current v ee = 0 v; v i =v cc or gnd v cc = 6.0 v - - ? 1.0 ? a v cc = 10.0 v - - ? 2.0 ? a i s(off) off-state leakage current v cc = 10.0 v; v ee = 0 v; v i =v ih or v il ; ?v sw ? =v cc ? v ee ; see figure 11 per channel - - ? 1.0 ? a all channels - - ? 1.0 ? a i s(on) on-state leakage current v i =v ih or v il ; ?v sw ? =v cc ? v ee ; v cc = 10.0 v; v ee = 0 v; see figure 12 -- ? 1.0 ? a i cc supply current v ee = 0 v; v i =v cc or gnd; v is =v ee or v cc ; v os =v cc or v ee v cc = 6.0 v - - 160.0 ? a v cc = 10.0 v - - 320.0 ? a table 7. static characte ristics for 74hc4053-q100 ?continued voltages are referenced to gnd (ground = 0 v). v is is the input voltage at pins nyn or nz, whichever is assigned as an input. v os is the output voltage at pins nz or nyn, whichever is assigned as an output. symbol parameter conditions min typ max unit table 8. static characteristics for 74hct4053-q100 voltages are referenced to gnd (ground = 0 v). v is is the input voltage at pins nyn or nz, whichever is assigned as an input. v os is the output voltage at pins nz or nyn, whichever is assigned as an output. symbol parameter conditions min typ max unit t amb =25 ?c v ih high-level input voltage v cc = 4.5 v to 5.5 v 2.0 1.6 - v v il low-level input voltage v cc = 4.5 v to 5.5 v - 1.2 0.8 v i i input leakage current v i =v cc or gnd; v cc = 5.5 v; v ee = 0 v - - ? 0.1 ? a i s(off) off-state leakage current v cc = 10.0 v; v ee = 0 v; v i =v ih or v il ; ?v sw ? =v cc ? v ee ; see figure 11 per channel - - ? 0.1 ? a all channels - - ? 0.1 ? a i s(on) on-state leakage current v cc = 10.0 v; v ee = 0 v; v i =v ih or v il ; ?v sw ? =v cc ? v ee ; see figure 12 -- ? 0.1 ? a i cc supply current v i =v cc or gnd; v is =v ee or v cc ; v os =v cc or v ee v cc = 5.5 v; v ee = 0 v - - 8.0 ? a v cc = 5.0 v; v ee = ? 5.0 v - - 16.0 ? a ? i cc additional supply current per input; v i =v cc ? 2.1 v; other inputs at v cc or gnd; v cc = 4.5 v to 5.5 v; v ee = 0 v - 50 180 ? a c i input capacitance - 3.5 - pf c sw switch capacitance independent pins nyn - 5 - pf common pins nz - 8 - pf
74hc_hct4053_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 2 ? 22 november 2012 12 of 30 nxp semiconductors 74hc4053-q100; 74hct4053-q100 triple 2-channel analog multiplexer/demultiplexer t amb = ? 40 ? cto+85 ?c v ih high-level input voltage v cc = 4.5 v to 5.5 v 2.0 - - v v il low-level input voltage v cc = 4.5 v to 5.5 v - - 0.8 v i i input leakage current v i =v cc or gnd; v cc = 5.5 v; v ee = 0 v - - ? 1.0 ? a i s(off) off-state leakage current v cc = 10.0 v; v ee = 0 v; v i =v ih or v il ; ?v sw ? =v cc ? v ee ; see figure 11 per channel - - ? 1.0 ? a all channels - - ? 1.0 ? a i s(on) on-state leakage current v cc = 10.0 v; v ee = 0 v; v i =v ih or v il ; ?v sw ? =v cc ? v ee ; see figure 12 -- ? 1.0 ? a i cc supply current v i =v cc or gnd; v is =v ee or v cc ; v os =v cc or v ee v cc = 5.5 v; v ee = 0 v - - 80.0 ? a v cc = 5.0 v; v ee = ? 5.0 v - - 160.0 ? a ? i cc additional supply current per input; v i =v cc ? 2.1 v; other inputs at v cc or gnd; v cc = 4.5 v to 5.5 v; v ee = 0 v - - 225 ? a t amb = ? 40 ? c to +125 ?c v ih high-level input voltage v cc = 4.5 v to 5.5 v 2.0 - - v v il low-level input voltage v cc = 4.5 v to 5.5 v - - 0.8 v i i input leakage current v i =v cc or gnd; v cc = 5.5 v; v ee = 0 v - - ? 1.0 ? a i s(off) off-state leakage current v cc = 10.0 v; v ee = 0 v; v i =v ih or v il ; ?v sw ? =v cc ? v ee ; see figure 11 per channel - - ? 1.0 ? a all channels - - ? 1.0 ? a i s(on) on-state leakage current v cc = 10.0 v; v ee = 0 v; v i =v ih or v il ; ?v sw ? =v cc ? v ee ; see figure 12 -- ? 1.0 ? a i cc supply current v i =v cc or gnd; v is =v ee or v cc ; v os =v cc or v ee v cc = 5.5 v; v ee = 0 v - - 160.0 ? a v cc = 5.0 v; v ee = ? 5.0 v - - 320.0 ? a ? i cc additional supply current per input; v i =v cc ? 2.1 v; other inputs at v cc or gnd; v cc = 4.5 v to 5.5 v; v ee = 0 v - - 245 ? a table 8. static characteristics for 74hct4053-q100 ?continued voltages are referenced to gnd (ground = 0 v). v is is the input voltage at pins nyn or nz, whichever is assigned as an input. v os is the output voltage at pins nz or nyn, whichever is assigned as an output. symbol parameter conditions min typ max unit
74hc_hct4053_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 2 ? 22 november 2012 13 of 30 nxp semiconductors 74hc4053-q100; 74hct4053-q100 triple 2-channel analog multiplexer/demultiplexer v is = v cc and v os = v ee . v is = v ee and v os = v cc . fig 11. test circuit for measuring off-state current 001aah827 nyn sn from select input nz gnd v ee v cc v is v os i sw a i sw a v is = v cc and v os = open-circuit. v is = v ee and v os = open-circuit. fig 12. test circuit for measuring on-state current i sw a 001aah828 nyn sn high from select input nz gnd v ee v cc v is v os
74hc_hct4053_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 2 ? 22 november 2012 14 of 30 nxp semiconductors 74hc4053-q100; 74hct4053-q100 triple 2-channel analog multiplexer/demultiplexer 11. dynamic characteristics table 9. dynamic characteristics for 74hc4053-q100 gnd = 0 v; t r =t f =6ns; c l = 50 pf; for test circuit see figure 15 . v is is the input voltage at a nyn or nz terminal, whichever is assigned as an input. v os is the output voltage at a nyn or nz termi nal, whichever is assigned as an output. symbol parameter conditions min typ max unit t amb =25 ?c t pd propagation delay v is to v os ; r l = ? ? ; see figure 13 [1] v cc = 2.0 v; v ee = 0 v - 15 60 ns v cc = 4.5 v; v ee =0 v - 5 12 ns v cc = 6.0 v; v ee =0 v - 4 10 ns v cc = 4.5 v; v ee = ? 4.5 v - 4 8 ns t on turn-on time e to v os ; r l = ?? ; see figure 14 [2] v cc = 2.0 v; v ee = 0 v - 60 220 ns v cc = 4.5 v; v ee = 0 v - 20 44 ns v cc = 5.0 v; v ee =0 v; c l = 15 pf - 17 - ns v cc = 6.0 v; v ee = 0 v - 16 37 ns v cc = 4.5 v; v ee = ? 4.5 v - 15 31 ns sn to v os ; r l = ?? ; see figure 14 [2] v cc = 2.0 v; v ee = 0 v - 75 220 ns v cc = 4.5 v; v ee = 0 v - 25 44 ns v cc = 5.0 v; v ee =0 v; c l = 15 pf - 21 - ns v cc = 6.0 v; v ee = 0 v - 20 37 ns v cc = 4.5 v; v ee = ? 4.5 v - 15 31 ns t off turn-off time e to v os ; r l =1 k ? ; see figure 14 [3] v cc = 2.0 v; v ee = 0 v - 63 210 ns v cc = 4.5 v; v ee = 0 v - 21 42 ns v cc = 5.0 v; v ee =0 v; c l = 15 pf - 18 - ns v cc = 6.0 v; v ee = 0 v - 17 36 ns v cc = 4.5 v; v ee = ? 4.5 v - 15 29 ns sn to v os ; r l =1 k ? ; see figure 14 [3] v cc = 2.0 v; v ee = 0 v - 60 210 ns v cc = 4.5 v; v ee = 0 v - 20 42 ns v cc = 5.0 v; v ee =0 v; c l = 15 pf - 17 - ns v cc = 6.0 v; v ee = 0 v - 16 36 ns v cc = 4.5 v; v ee = ? 4.5 v - 15 29 ns c pd power dissipation capacitance per switch; v i = gnd to v cc [4] -36- pf
74hc_hct4053_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 2 ? 22 november 2012 15 of 30 nxp semiconductors 74hc4053-q100; 74hct4053-q100 triple 2-channel analog multiplexer/demultiplexer t amb = ? 40 ? cto+85 ?c t pd propagation delay v is to v os ; r l = ? ? ; see figure 13 [1] v cc = 2.0 v; v ee =0 v - - 75 ns v cc = 4.5 v; v ee =0 v - - 15 ns v cc = 6.0 v; v ee =0 v - - 13 ns v cc = 4.5 v; v ee = ? 4.5 v - - 10 ns t on turn-on time e to v os ; r l = ?? ; see figure 14 [2] v cc = 2.0 v; v ee =0 v - - 275 ns v cc = 4.5 v; v ee =0 v - - 55 ns v cc = 6.0 v; v ee =0 v - - 47 ns v cc = 4.5 v; v ee = ? 4.5 v - - 39 ns sn to v os ; r l = ?? ; see figure 14 [2] v cc = 2.0 v; v ee =0 v - - 275 ns v cc = 4.5 v; v ee =0 v - - 55 ns v cc = 6.0 v; v ee =0 v - - 47 ns v cc = 4.5 v; v ee = ? 4.5 v - - 39 ns t off turn-off time e to v os ; r l =1 k ? ; see figure 14 [3] v cc = 2.0 v; v ee =0 v - - 265 ns v cc = 4.5 v; v ee =0 v - - 53 ns v cc = 6.0 v; v ee =0 v - - 45 ns v cc = 4.5 v; v ee = ? 4.5 v - - 36 ns sn to v os ; r l =1 k ? ; see figure 14 [3] v cc = 2.0 v; v ee =0 v - - 265 ns v cc = 4.5 v; v ee =0 v - - 53 ns v cc = 6.0 v; v ee =0 v - - 45 ns v cc = 4.5 v; v ee = ? 4.5 v - - 36 ns t amb = ? 40 ? c to +125 ?c t pd propagation delay v is to v os ; r l = ? ? ; see figure 13 [1] v cc = 2.0 v; v ee =0 v - - 90 ns v cc = 4.5 v; v ee =0 v - - 18 ns v cc = 6.0 v; v ee =0 v - - 15 ns v cc = 4.5 v; v ee = ? 4.5 v - - 12 ns table 9. dynamic characteristics for 74hc4053-q100 ?continued gnd = 0 v; t r =t f =6ns; c l = 50 pf; for test circuit see figure 15 . v is is the input voltage at a nyn or nz terminal, whichever is assigned as an input. v os is the output voltage at a nyn or nz termi nal, whichever is assigned as an output. symbol parameter conditions min typ max unit
74hc_hct4053_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 2 ? 22 november 2012 16 of 30 nxp semiconductors 74hc4053-q100; 74hct4053-q100 triple 2-channel analog multiplexer/demultiplexer [1] t pd is the same as t phl and t plh . [2] t on is the same as t pzh and t pzl . [3] t off is the same as t phz and t plz . [4] c pd is used to determine the dynamic power dissipation (p d in ? w). p d = c pd ? v cc 2 ? f i ? n + ? {(c l +c sw ) ? v cc 2 ? f o } where: f i = input frequency in mhz; f o = output frequency in mhz; n = number of inputs switching; ? {(c l +c sw ) ? v cc 2 ? f o } = sum of outputs; c l = output load capacitance in pf; c sw = switch capacitance in pf; v cc = supply voltage in v. t on turn-on time e to v os ; r l = ?? ; see figure 14 [2] v cc = 2.0 v; v ee =0 v - - 330 ns v cc = 4.5 v; v ee =0 v - - 66 ns v cc = 6.0 v; v ee =0 v - - 56 ns v cc = 4.5 v; v ee = ? 4.5 v - - 47 ns sn to v os ; r l = ?? ; see figure 14 [2] v cc = 2.0 v; v ee =0 v - - 330 ns v cc = 4.5 v; v ee =0 v - - 66 ns v cc = 6.0 v; v ee =0 v - - 56 ns v cc = 4.5 v; v ee = ? 4.5 v - - 47 ns t off turn-off time e to v os ; r l =1 k ? ; see figure 14 [3] v cc = 2.0 v; v ee =0 v - - 315 ns v cc = 4.5 v; v ee =0 v - - 63 ns v cc = 6.0 v; v ee =0 v - - 54 ns v cc = 4.5 v; v ee = ? 4.5 v - - 44 ns sn to v os ; r l =1 k ? ; see figure 14 [3] v cc = 2.0 v; v ee =0 v - - 315 ns v cc = 4.5 v; v ee =0 v - - 63 ns v cc = 6.0 v; v ee =0 v - - 54 ns v cc = 4.5 v; v ee = ? 4.5 v - - 44 ns table 9. dynamic characteristics for 74hc4053-q100 ?continued gnd = 0 v; t r =t f =6ns; c l = 50 pf; for test circuit see figure 15 . v is is the input voltage at a nyn or nz terminal, whichever is assigned as an input. v os is the output voltage at a nyn or nz termi nal, whichever is assigned as an output. symbol parameter conditions min typ max unit
74hc_hct4053_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 2 ? 22 november 2012 17 of 30 nxp semiconductors 74hc4053-q100; 74hct4053-q100 triple 2-channel analog multiplexer/demultiplexer table 10. dynamic characteristics for 74hct4053-q100 gnd = 0 v; t r =t f =6ns; c l = 50 pf; for test circuit see figure 15 . v is is the input voltage at a nyn or nz terminal, whichever is assigned as an input. v os is the output voltage at a nyn or nz termi nal, whichever is assigned as an output. symbol parameter conditions min typ max unit t amb =25 ?c t pd propagation delay v is to v os ; r l = ?? ; see figure 13 [1] v cc = 4.5 v; v ee =0 v - 5 12 ns v cc = 4.5 v; v ee = ? 4.5 v - 4 8 ns t on turn-on time e to v os ; r l =1 k ? ; see figure 14 [2] v cc = 4.5 v; v ee = 0 v - 27 48 ns v cc = 5.0 v; v ee =0 v; c l = 15 pf - 23 - ns v cc = 4.5 v; v ee = ? 4.5 v - 16 34 ns sn to v os ; r l =1 k ? ; see figure 14 [2] v cc = 4.5 v; v ee = 0 v - 25 48 ns v cc = 5.0 v; v ee =0 v; c l = 15 pf - 21 - ns v cc = 4.5 v; v ee = ? 4.5 v - 16 34 ns t off turn-off time e to v os ; r l =1 k ? ; see figure 14 [3] v cc = 4.5 v; v ee = 0 v - 24 44 ns v cc = 5.0 v; v ee =0 v; c l = 15 pf - 20 - ns v cc = 4.5 v; v ee = ? 4.5 v - 15 31 ns sn to v os ; r l =1 k ? ; see figure 14 [3] v cc = 4.5 v; v ee = 0 v - 22 44 ns v cc = 5.0 v; v ee =0 v; c l = 15 pf - 19 - ns v cc = 4.5 v; v ee = ? 4.5 v - 15 31 ns c pd power dissipation capacitance per switch; v i = gnd to v cc ? 1.5 v [4] -36- pf t amb = ? 40 ? cto+85 ?c t pd propagation delay v is to v os ; r l = ?? ; see figure 13 [1] v cc = 4.5 v; v ee =0 v --15ns v cc = 4.5 v; v ee = ? 4.5 v - - 10 ns t on turn-on time e to v os ; r l =1 k ? ; see figure 14 [2] v cc = 4.5 v; v ee =0 v --60ns v cc = 4.5 v; v ee = ? 4.5 v - - 43 ns sn to v os ; r l =1 k ? ; see figure 14 [2] v cc = 4.5 v; v ee =0 v --60ns v cc = 4.5 v; v ee = ? 4.5 v - - 43 ns t off turn-off time e to v os ; r l =1 k ? ; see figure 14 [3] v cc = 4.5 v; v ee =0 v --55ns v cc = 4.5 v; v ee = ? 4.5 v - - 39 ns sn to v os ; r l =1 k ? ; see figure 14 [3] v cc = 4.5 v; v ee =0 v --55ns v cc = 4.5 v; v ee = ? 4.5 v - - 39 ns
74hc_hct4053_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 2 ? 22 november 2012 18 of 30 nxp semiconductors 74hc4053-q100; 74hct4053-q100 triple 2-channel analog multiplexer/demultiplexer [1] t pd is the same as t phl and t plh . [2] t on is the same as t pzh and t pzl . [3] t off is the same as t phz and t plz . [4] c pd is used to determine the dynamic power dissipation (p d in ? w). p d = c pd ? v cc 2 ? f i ? n + ? {(c l +c sw ) ? v cc 2 ? f o } where: f i = input frequency in mhz; f o = output frequency in mhz; n = number of inputs switching; ? {(c l +c sw ) ? v cc 2 ? f o } = sum of outputs; c l = output load capacitance in pf; c sw = switch capacitance in pf; v cc = supply voltage in v. t amb = ? 40 ? c to +125 ?c t pd propagation delay v is to v os ; r l = ?? ; see figure 13 [1] v cc = 4.5 v; v ee =0 v --18ns v cc = 4.5 v; v ee = ? 4.5 v - - 12 ns t on turn-on time e to v os ; r l =1 k ? ; see figure 14 [2] v cc = 4.5 v; v ee =0 v --72ns v cc = 4.5 v; v ee = ? 4.5 v - - 51 ns sn to v os ; r l =1 k ? ; see figure 14 [2] v cc = 4.5 v; v ee =0 v --72ns v cc = 4.5 v; v ee = ? 4.5 v - - 51 ns t off turn-off time e to v os ; r l =1 k ? ; see figure 14 [3] v cc = 4.5 v; v ee =0 v --66ns v cc = 4.5 v; v ee = ? 4.5 v - - 47 ns sn to v os ; r l =1 k ? ; see figure 14 [3] v cc = 4.5 v; v ee =0 v --66ns v cc = 4.5 v; v ee = ? 4.5 v - - 47 ns table 10. dynamic characteristics for 74hct4053-q100 ?continued gnd = 0 v; t r =t f =6ns; c l = 50 pf; for test circuit see figure 15 . v is is the input voltage at a nyn or nz terminal, whichever is assigned as an input. v os is the output voltage at a nyn or nz termi nal, whichever is assigned as an output. symbol parameter conditions min typ max unit fig 13. input (v is ) to output (v os ) propagation delays 001aad555 t plh t phl 50 % 50 % v is input v os output
74hc_hct4053_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 2 ? 22 november 2012 19 of 30 nxp semiconductors 74hc4053-q100; 74hct4053-q100 triple 2-channel analog multiplexer/demultiplexer for 74hc4053-q100: v m =0.5 ? v cc . for 74hct4053-q100: v m =1.3v. fig 14. turn-on and turn-off times 001aad556 t plz t phz switch off switch on switch on v os output v os output e, sn inputs v m v i 0 v 90 % 10 % t pzl t pzh 50 % 50 % definitions for test circuit; see table 11 : r t = termination resistance should be equal to the output impedance z o of the pulse generator. c l = load capacitance including jig and probe capacitance. r l = load resistance. s1 = test selection switch. fig 15. test circuit for measuring switching times v m v m t w t w 10 % 90 % 0 v v i v i negative pulse positive pulse 0 v v m v m 90 % 10 % t f t r t r t f 001aae382 v cc v cc open gnd v ee v i v os dut c l r t r l s1 pulse generator v is
74hc_hct4053_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 2 ? 22 november 2012 20 of 30 nxp semiconductors 74hc4053-q100; 74hct4053-q100 triple 2-channel analog multiplexer/demultiplexer [1] t r = t f = 6 ns; when measuring f max , there is no constraint to t r and t f with 50 % duty factor. [2] v i values: a) for 74hc4053-q100: v i = v cc b) for 74hct4053-q100: v i = 3 v 11.1 additional dynami c characteristics [1] adjust input voltage v is to 0 dbm level (0 dbm = 1 mw into 600 ? ). [2] adjust input voltage v is to 0 dbm level at v os for 1 mhz (0 dbm = 1 mw into 50 ? ). table 11. test data test input load s1 position v i v is t r , t f c l r l at f max other [1] t phl , t plh [2] pulse < 2 ns 6 ns 50 pf 1 k ? open t pzh , t phz [2] v cc < 2 ns 6 ns 50 pf 1 k ? v ee t pzl , t plz [2] v ee < 2 ns 6 ns 50 pf 1 k ? v cc table 12. additional dynamic characteristics recommended conditions and typical values; gnd = 0 v; t amb =25 ? c; c l =50pf. v is is the input voltage at pins nyn or nz, whichever is assigned as an input. v os is the output voltage at pins nyn or nz, whichever is assigned as an output. symbol parameter conditions min typ max unit d sin sine-wave distortion f i = 1 khz; r l =10k ? ; see figure 16 v is = 4.0 v (p-p); v cc = 2.25 v; v ee = ? 2.25 v - 0.04 - % v is = 8.0 v (p-p); v cc = 4.5 v; v ee = ? 4.5 v - 0.02 - % f i =10khz; r l =10k ? ; see figure 16 v is = 4.0 v (p-p); v cc = 2.25 v; v ee = ? 2.25 v - 0.12 - % v is = 8.0 v (p-p); v cc = 4.5 v; v ee = ? 4.5 v - 0.06 - % ? iso isolation (off-state) r l = 600 ? ; f i = 1 mhz; see figure 17 v cc = 2.25 v; v ee = ? 2.25 v [1] - ? 50 - db v cc = 4.5 v; v ee = ? 4.5 v [1] - ? 50 - db xtalk crosstalk between two switches/multiplexers; r l = 600 ? ; f i = 1 mhz; see figure 18 v cc = 2.25 v; v ee = ? 2.25 v [1] - ? 60 - db v cc = 4.5 v; v ee = ? 4.5 v [1] - ? 60 - db v ct crosstalk voltage peak-to-peak value between control and any switch. r l =600 ? ; f i = 1 mhz; e or sn square wave between v cc and gnd; t r =t f =6ns; see figure 19 v cc = 4.5 v; v ee =0 v - 110 - mv v cc = 4.5 v; v ee = ? 4.5 v - 220 - mv f ( ? 3db) ? 3 db frequency response r l =50 ? ; see figure 20 v cc = 2.25 v; v ee = ? 2.25 v [2] -160- mhz v cc = 4.5 v; v ee = ? 4.5 v [2] -170- mhz
74hc_hct4053_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 2 ? 22 november 2012 21 of 30 nxp semiconductors 74hc4053-q100; 74hct4053-q100 triple 2-channel analog multiplexer/demultiplexer fig 16. test circuit for measuring sine-wave distortion db 001aah829 nyn/nz 10 f v is v os nz/nyn c l r l sn gnd v ee v cc v cc = 4.5 v; gnd = 0 v; v ee = ? 4.5 v; r l = 600 ? ; r s =1k ? . a. test circuit b. isolation (off-state) as a function of frequency fig 17. test circuit for measuring isolation (off-state) db 001aah871 nyn/nz 0.1 f v is v os nz/nyn c l r l sn gnd v ee v cc 001aae332 f i (khz) 10 10 5 10 6 10 4 10 2 10 3 ?60 ?40 ?80 ?20 0 iso (db) ?100
74hc_hct4053_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 2 ? 22 november 2012 22 of 30 nxp semiconductors 74hc4053-q100; 74hct4053-q100 triple 2-channel analog multiplexer/demultiplexer fig 18. test circuits for measuring crosst alk between any two sw itches/multiplexers db 001aah873 nyn/nz v os nz/nyn c l r l r l sn gnd v ee v cc nyn/nz 0.1 f v is nz/nyn c l r l r l sn gnd v ee v cc fig 19. test circuit for measuring crosst alk between control input and any switch oscilloscope 001aah913 nyn v ct nz 2r l 2r l 2r l 2r l sn, e gnd v ee v cc g
74hc_hct4053_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 2 ? 22 november 2012 23 of 30 nxp semiconductors 74hc4053-q100; 74hct4053-q100 triple 2-channel analog multiplexer/demultiplexer v cc = 4.5 v; gnd = 0 v; v ee = ? 4.5 v; r l =50 ? ; r s =1k ? . a. test circuit b. typical frequency response fig 20. test circuit for frequency response db 001aah829 nyn/nz 10 f v is v os nz/nyn c l r l sn gnd v ee v cc 001aad551 f (khz) 10 10 5 10 6 10 4 10 2 10 3 ?1 1 ?3 3 5 v os (db) ?5
74hc_hct4053_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 2 ? 22 november 2012 24 of 30 nxp semiconductors 74hc4053-q100; 74hct4053-q100 triple 2-channel analog multiplexer/demultiplexer 12. package outline fig 21. package outline sot109-1 (so16) x w m a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 8 9 1 16 y pin 1 index unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 sot109-1 99-12-27 03-02-19 076e07 ms-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.39 0.38 0.16 0.15 0.05 1.05 0.041 0.244 0.228 0.028 0.020 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 0 2.5 5 mm scale so16: plastic small outline package; 16 leads; body width 3.9 mm sot109-1
74hc_hct4053_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 2 ? 22 november 2012 25 of 30 nxp semiconductors 74hc4053-q100; 74hct4053-q100 triple 2-channel analog multiplexer/demultiplexer fig 22. package outline sot403-1 (tssop16) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.40 0.06 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot403-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 18 16 9 a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 a max. 1.1 pin 1 index
74hc_hct4053_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 2 ? 22 november 2012 26 of 30 nxp semiconductors 74hc4053-q100; 74hct4053-q100 triple 2-channel analog multiplexer/demultiplexer fig 23. package outline sot763-1 (dhvqfn16) terminal 1 index area 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 3.6 3.4 d h 2.15 1.85 y 1 2.6 2.4 1.15 0.85 e 1 2.5 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot763-1 mo-241 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot763-1 dhvqfn16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 27 15 10 9 8 1 16 x d e c b a terminal 1 index area ac c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1) 02-10-17 03-01-27
74hc_hct4053_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 2 ? 22 november 2012 27 of 30 nxp semiconductors 74hc4053-q100; 74hct4053-q100 triple 2-channel analog multiplexer/demultiplexer 13. abbreviations 14. revision history table 13. abbreviations acronym description cmos complementary metal-oxide semiconductor esd electrostatic discharge hbm human body model mm machine model mil military table 14. revision history document id release date data sheet status change notice supersedes 74hc_hct4053_q100 v.2 20121122 product data sheet - 74hc_hct4053_q100 v.1 modifications: ? cdm added to features. 74hc_hct4053_q100 v.1 20120720 product data sheet - -
74hc_hct4053_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 2 ? 22 november 2012 28 of 30 nxp semiconductors 74hc4053-q100; 74hct4053-q100 triple 2-channel analog multiplexer/demultiplexer 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 15.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 15.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use in automotive applications ? this nxp semiconductors product has been qualified for use in automotive applications. unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
74hc_hct4053_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 2 ? 22 november 2012 29 of 30 nxp semiconductors 74hc4053-q100; 74hct4053-q100 triple 2-channel analog multiplexer/demultiplexer no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any licens e under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 15.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 16. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors 74hc4053-q100; 74hct4053-q100 triple 2-channel analog multiplexer/demultiplexer ? nxp b.v. 2012. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 22 november 2012 document identifier: 74hc_hct4053_q100 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 functional description . . . . . . . . . . . . . . . . . . . 5 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 recommended operating conditions. . . . . . . . 6 10 static characteristics. . . . . . . . . . . . . . . . . . . . . 7 11 dynamic characteristics . . . . . . . . . . . . . . . . . 14 11.1 additional dynamic characteristics . . . . . . . . . 20 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 24 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 27 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . 27 15 legal information. . . . . . . . . . . . . . . . . . . . . . . 28 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 28 15.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 15.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 15.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 29 16 contact information. . . . . . . . . . . . . . . . . . . . . 29 17 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

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